The disclosed invention generally relates to digital-to-analog converters and is particularly directed to a segmented pulse width modulated (PWM) digital-to-analog (D/A) converter having parallel conversion stages.
D/A converters are utilized to provide an analog signal, such as a voltage, as function of a digital input. For example, certain information may be digitally processed and then converted for use with analog processing circuitry. Particular examples of such applications of D/A converters include compact laser disc players, multiplexed aircraft audio systems, and instrumentation applications
Pulse width modulated (PWM) D/A converters typically include a pulse width modulator which provides a pulse width modulated signal having pulses with respective widths (and areas) that are proportional to the input digital signal. The output of the pulse width modulator is provided to an integrator which generally functions as a low pass filter. The integrator output is an analog signal which has a characteristic (e.g., voltage) that is proportional to the pulse width modulated signal, and is therefore proportional to the digital input signal.
Typically, the modulated pulses are provided by the output of a flip-flop that is controlled by a resettable counter and a comparator. At the beginning of each pulse period the counter starts counting and the flip-flop is set to provide a high output for a non-zero N-bit digital input. The flip-flop output remains high until the counter output corresponds to the digital input, at which time the flip-flop is reset. The counter has a maximum count equal to the maximum value 2.sup.N of the digital input, and such maximum count must be reached within the pulse period. Thus, the counter clock must be at least as fast as the pulse rate multiplied by the maximum digital input value 2.sup.N.
Generally, the output pulses are provided at a fixed pulse rate (which is also the conversion rate) so that the start of each pulse (including a pulse of zero width and area) is periodic. Such pulse rate may be equal to the rate at which digital values are provided to the pulse width modulator (the digital input rate), whereby each digital input is converted once. However, it is well known for pulse width modulation systems that a pulse rate that is close to the spectral content of the analog signal of interest creates distortion in such analog signal. Additionally, the time constant of the integrator cannot be too small in comparison to the pulse period since too small a time constant would result in excessive ripple. However, a longer time constant reduces the high frequency response of the D/A converter.
A known technique for avoiding the foregoing problems is the use of a pulse rate that is higher than the digital input rate, whereby each digital input is converted more than once (i.e., used to modulate more than one pulse). The integrator time constant is accordingly reduced. However, an increased pulse rate also requires an increased counter clock rate for the pulse width modulator.
For example, for a 10 bit digital input provided at a 30 KHz rate and converted with a 30 KHz pulse rate (i.e., each input value is used to modulate only one pulse), a counter clock rate of 30.72 MHz is required. Increasing the pulse rate by a factor of 5 to 150 KHz to avoid distortion would require a counter clock rate of 153.6 MHz. It should therefore be readily apparent that PWM D/A conversion with known techniques has limitations as to digital input frequencies. Additionally, with known PWM D/A conversion the required clock rates increase dramatically with increased digital input rates.
U.S. Pat. No. 4,233,591, issued to Murata et al. on Nov. 11, 1980, apparently provides for an effectively increased pulse rate by dividing the pulse for each input into several pulses that are distributed over a single pulse period. However, the system of the '591 patent still requires a counter clock rate equal to the digital input rate times 2.sup.N for an N-bit input.